Processor Architecture¶
Cache¶
Challenge: Managing shared cache resources (e.g. LLC) efficiently in multi-core/multi-programmed environments.
| Year | Venue | Authors | Title | Tags | P | E | N |
|---|---|---|---|---|---|---|---|
| 2011 | ISCA | Stanford | Vantage: Scalable and Efficient Fine-Grain Cache Partitioning | managed-unmanaged region division; churn-based management; feedback-based aperture control | |||
| 2018 | EuroSys | PKU | DCAPS: dynamic cache allocation with partial sharing | dynamic fine-grained shared cache management; balance cache utilization and contention; online practical miss rate curve | |||
| 2021 | ISCA | EPFL | Large-Scale Graph Processing on FPGAs with Caches for Thousands of Simultaneous Misses | miss-optimized memory system (MOMS); extreme non-blocking cache; two-level MOMS architecture; caches for irregular accesses | 4 | 4 | 4 |
| 2024 | MICRO | Sungkyunkwan University | CacheCraft: Enhancing GPU Performance under Memory Protection through Reconstructed Caching | reconstructed caching; memory-oriented sector size; single-access in-band ECC; balanced memory layout for mixed-size sectors | 3 | 3 | 2 |
| 2025 | ISCA | UW-Madison | The XOR Cache: A Catalyst for Compression | XOR compression; cache inclusion redundancy; inter-line & intra-line synergy; map table for pairing | 4 | 3 | 4 |
Multi-Level Cache¶
Challenge: Optimizing the interaction and data movement between different levels of the cache hierarchy (e.g. L1 - L2 - L3) in Chip Multi-Processors is complex.
| Year | Venue | Authors | Title | Tags | P | E | N |
|---|---|---|---|---|---|---|---|
| 2005 | ISCA | IBM | Adaptive mechanisms and policies for managing cache hierarchies in chip multiprocessors | limit unnecessary clean write backs; write back L2 to peer L2; second adaptive mechanism | |||
| 2012 | JIP | Tokio Tech | Autonomous L3 Cache Technolgy for High Responsiveness | autonomous L3 cache; trio-configuration architecture; autonomous decentralized multi-layer cache |
Vector Unit¶
Memory Access¶
Challenge: Vector memory access is not well supported & optimized in the current microarchitecture like RISC-V.
| Year | Venue | Authors | Title | Tags | P | E | N |
|---|---|---|---|---|---|---|---|
| 2025 | CF Companion | ETHZ | AraOS: Analyzing the Impact of Virtual Memory Management on Vector Unit Performance | virtual memory management for RVV; performance analysis of virtual memory overhead | 2 | 2 | 1 |
| 2025 | arXiv | THU | Efficient Architecture for RISC-V Vector Memory Access | data reorganization module; load/store data organization; row/column-accessible vector register file | 2 | 4 | 3 |